In this quiz, I am going to create two multiplexers. The first one is implemented using an if statement inside an always block, while the second one is implemented using an assign statement.
The condition is that if both sel_b1 and sel_b2 are true, the output will be the result of input b; otherwise, the output will be the result of input a.
Here is my code for this quiz:
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always
);
always @(*) begin
if ((sel_b1 == 1) & (sel_b2 == 1))
out_always = b;
else
out_always = a;
end
assign out_assign = ((sel_b1 == 1) & (sel_b2 == 1)) ? b : a;
endmodule
