In this quiz, we are required to write Verilog code to create a 6-to-1 multiplexer. If the sel input is 000, data0 is driven to the output. If the sel input is 001, data1 is driven to the output, and so on.
For values from 0 to 5, we simply apply the fundamental principle of multiplexer operation. However, for values 6 and 7, the output is assigned to 0, as required by the quiz.
The statement default: out = 3'b000; means that if sel has any other value, the output will be set to 0.
Here is my code for this quiz:
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out );//
always@(*) begin // This is a combinational circuit
case(sel)
3’b000 : out = data0;
3’b001 : out = data1;
3’b010 : out = data2;
3’b011 : out = data3;
3’b100 : out = data4;
3’b101 : out = data5;
default : out = 4’b0000;
endcase
end
endmodule
Reference: https://hdlbits.01xz.net/wiki/Always_case.
