HDL-Bits: Module_addsub

In this quiz, I created an adder-subtractor circuit as shown in the diagram. The add16 module was already provided, so my task was to instantiate two of them and connect them using internal wires and input/output ports.

First, I instantiated two add16 modules using the keywords add16 instance1 and add16 instance2.

Next, I connected the two modules through their input/output ports and an internal wire. To connect the cout port from the first add16 module to the cin port of the second module, I created a wire called wire1.

The most challenging part of this quiz was creating the XOR expression between the 32-bit input b and the 1-bit input sub. This requires replicating the sub signal 32 times. The replication operator {32{sub}} can be used for this purpose. However, since each add16 module handles only 16 bits, the signal must be split into two 16-bit parts.

Finally, here is my code for this quiz, which successfully passed the simulation:

module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire wire1;

add16 instance1 ( .a(a[15:0]), .b( b[15:0]^({16{sub}}) ), .sum(sum[15:0]), .cout(wire1) , .cin(sub) );
add16 instance2 ( .a(a[31:16]), .b( b[31:16]^({16{sub}}) ), .sum(sum[31:16]), .cin(wire1) );
endmodule

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