In this quiz, I was required to write a verilog code to create a 100-bit wide, 2-to-1 multiplexer. This is as simple as creating a multiplexing circuit.
Here is my code for this quiz.
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
always@(*)begin
case(sel)
1’b0 : out = a;
1’b1 : out = b;
endcase
end
endmodule
Reference: https://hdlbits.01xz.net/wiki/Mux2to1v
