HDL-Bits Solution: 4 instances of adder

In this quiz, I was required to create a series of 1-bit full adders, which required me to instantiate four of them. For the first full adder module, I assigned ‘cin’ to logic 0. In the fourth adder module, the ‘cout’ signal is assigned to the ‘sum[4]’ signal. I also declared three wire signals which were used to connect the full adder modules together.

Here is my code for this quiz

module full_adder (
input a, b, cin,
output s, cout
);
assign s = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule

module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum);

wire wire1, wire2, wire3;

full_adder FA1 ( .a(x[0]), .b(y[0]), .s(sum[0]), .cin(1’b0), .cout(wire1) );
full_adder FA2 ( .a(x[1]), .b(y[1]), .s(sum[1]), .cin(wire1), .cout(wire2) );
full_adder FA3 ( .a(x[2]), .b(y[2]), .s(sum[2]), .cin(wire2), .cout(wire3) );
full_adder FA4 ( .a(x[3]), .b(y[3]), .s(sum[3]), .cin(wire3), .cout(sum[4]) );

endmodule

reference:https://hdlbits.01xz.net/wiki/Exams/m2014_q4j

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