HDL-Bits Solution : Another Gate

In this quiz, I was required to create the gate as shown in the picture below. For this quiz, I used a logical operator, as there is only one gate that needs to be created.

Here is my code.

module top_module (
    input in1,
    input in2,
    output out);
    
    assign out = (in1&&(!in2));
 
endmodule

 

Reference : https://hdlbits.01xz.net/wiki/Exams/m2014_q4f

Leave a Reply

Your email address will not be published. Required fields are marked *